Session

DescriptionThe increasing complexity of SoC designs, coupled with the high cost of a re-spin due to functional bugs, requires constant innovation in verification techniques and methodologies to ensure first pass silicon success. This session discusses a collection of such techniques spanning automated methods to create simplified test cases for tool bugs, use of symbolic simulation for the verification of interface IP, protocol validation of high speed serial links, power estimation and tracking using real world use cases, fast and efficient methodology for multi-PVT corner validation, and a formal verification framework for DDR5 power management features.