Presentation
3DIC Design Ecosystem – The Cats That Need Herding!
DescriptionAt the end of 2D scaling of Moore's law, 3D integrated circuits that take advantages of advanced packaging and heterogeneous integration offers many prospects of extending the chip density scaling and the system performance improvements for the next decade. Much of 3DIC design activity in the industry today is done via different teams within the same chipmaker company. 3DICs hold the potential to not only make the chip architecture heterogeneous, and chiplet sourcing to be highly diversified. Moreover, 3DICs themselves have a few avenues to be realized towards commercial success, ranging from true disaggregated chiplets to sequential stacked processing. This presses us to answer a few key questions:
1. Technology:
a. How will heat dissipation be managed, are new cooling techniques are being pursued to mitigate the thermal challenge?
b. How to design the power delivery network from the board to the substrate to the multi-tier of 3D stack with minimal voltage drop and high-power conversion efficiency? How to design the backside power delivery in leading edge node CMOS with 3D stacking?
c. How to ensure signal integrity, yield and reliability between multiple tiers of 3D stacking, and what testing and standardization efforts are needed to embrace the heterogeneous dies from different designers and foundries?
2. EDA flows and interoperability
a. Will the ecosystem extend the same standards-based interoperability of design tools, flows and methodologies to 3DIC, as enjoyed by monolithic system designers today?
b. How can EDA industry help system designers in planning, managing and tracking their complex 3DIC projects in implementation, analysis, and signoffs?
3. Roadmap:
a. Is the roadmap to sequential monolithic stacked 3DIC an inevitability? What factors lead the industry to it?
b. What are the boundaries between monolithic 3D integration (with sequential processing at BEOL) and heterogenous 3D integration (with die stacking or bonding)?
Are we as an industry able to apply lessons from the past struggles with monolithic chip design and interoperability to this emerging challenge? This panel will discuss the need, scope of solution and potential candidate efforts already in motion.
1. Technology:
a. How will heat dissipation be managed, are new cooling techniques are being pursued to mitigate the thermal challenge?
b. How to design the power delivery network from the board to the substrate to the multi-tier of 3D stack with minimal voltage drop and high-power conversion efficiency? How to design the backside power delivery in leading edge node CMOS with 3D stacking?
c. How to ensure signal integrity, yield and reliability between multiple tiers of 3D stacking, and what testing and standardization efforts are needed to embrace the heterogeneous dies from different designers and foundries?
2. EDA flows and interoperability
a. Will the ecosystem extend the same standards-based interoperability of design tools, flows and methodologies to 3DIC, as enjoyed by monolithic system designers today?
b. How can EDA industry help system designers in planning, managing and tracking their complex 3DIC projects in implementation, analysis, and signoffs?
3. Roadmap:
a. Is the roadmap to sequential monolithic stacked 3DIC an inevitability? What factors lead the industry to it?
b. What are the boundaries between monolithic 3D integration (with sequential processing at BEOL) and heterogenous 3D integration (with die stacking or bonding)?
Are we as an industry able to apply lessons from the past struggles with monolithic chip design and interoperability to this emerging challenge? This panel will discuss the need, scope of solution and potential candidate efforts already in motion.
Event Type
Research Panel
TimeWednesday, June 263:30pm - 5:30pm PDT
Location3014, 3rd Floor
Design