Presentation
Blackout – Managing kW Power Budgets
DescriptionSoCs designed for compute-intensive workloads, such as AI training and inferencing, continue to grow and power budgets are increasing geometrically. Handling these power budgets from an SoC and system perspective requires rigorous tools, flows, and methodologies. The question that remains is how these burgeoning power budgets impact broader systems and system-of-system effects, and what role does silicon IP play in shaping these outcomes.
2.5D and 3D solutions are emerging as potential mitigators for the expanding power budgets, but the extent of their effect is yet to be fully understood. Additionally, with the constant evolution and growth in technology, there is a looming question: will power budgets level off or continue on a path of exponential growth? The influence of silicon IP in directing this trajectory is a topic of keen interest.
A significant player in this dynamic is the role of next-generation VRMs. With their potential to regulate voltage and hence influence power, they might hold the answer to managing the surge in power budgets. This conference seeks to explore their impact, dissect the role of silicon IP, and generate insightful discussions on the future of power consumption within technology. Together, we will answer some of the following questions from an EDA, system, IP, and SoC design perspective:
o What are the primary factors driving the immense leaps in on-die power?
o What tools, flows, and methodologies are required to manage SoC and system power budgets? o What are the system and system-of-system effects of ballooning power budgets?
o What effect will 2.5D and 3D solutions have on growing power budgets?
o Will we see a leveling off in power budgets or will they keep growing exponentially? And why? o What is the role of next-generation VRMs
2.5D and 3D solutions are emerging as potential mitigators for the expanding power budgets, but the extent of their effect is yet to be fully understood. Additionally, with the constant evolution and growth in technology, there is a looming question: will power budgets level off or continue on a path of exponential growth? The influence of silicon IP in directing this trajectory is a topic of keen interest.
A significant player in this dynamic is the role of next-generation VRMs. With their potential to regulate voltage and hence influence power, they might hold the answer to managing the surge in power budgets. This conference seeks to explore their impact, dissect the role of silicon IP, and generate insightful discussions on the future of power consumption within technology. Together, we will answer some of the following questions from an EDA, system, IP, and SoC design perspective:
o What are the primary factors driving the immense leaps in on-die power?
o What tools, flows, and methodologies are required to manage SoC and system power budgets? o What are the system and system-of-system effects of ballooning power budgets?
o What effect will 2.5D and 3D solutions have on growing power budgets?
o Will we see a leveling off in power budgets or will they keep growing exponentially? And why? o What is the role of next-generation VRMs
Moderator
Event Type
DAC Pavilion Panel
TimeTuesday, June 252:00pm - 2:45pm PDT
LocationDAC Pavilion, Level 2 Exhibit Hall
Design