Presentation
Methodology to define, design and support ultra-low voltage Digital Design
DescriptionWith demand for aggressive reduction in power budget, among other techniques, supply voltage scaling to the lowest possible levels still remains the simplest yet most effective solution for both dynamic and static power reduction. In this paper, we discuss the existing techniques to enable low voltage digital designs and propose a comprehensive method to define necessary voltage levels that helps the design team to take an informed decision on what the lowest supply voltage they should go to for reliable operation. At the same time, this ensures the functional robustness of the design along with accurate timing closure at ultra-low voltage. Extensive data is presented for a design at 65nm process node for each phase of the design proposed in this paper.
Event Type
Work-in-Progress Poster
TimeTuesday, June 256:00pm - 7:00pm PDT
LocationLevel 2 Lobby
AI
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