Presentation
A Novel Approach: Applying Fractional Factorial Design Methodology to Stress-Map, Experimental Study for Stress-Induced Failure (Bug), and Stress Coverage Assessment in Post-Silicon Validation Process
DescriptionPrior to product market launch, it is critical to have a cost-effective post-silicon validation program. Currently, post-silicon validation requires tremendous resources to constantly stress test post silicon by running a list of internal and external tools across a cluster of systems. This effort involves a high number of stress-test cases and consumes thousands of stress hours. However, the question remains, are the parts really being stressed by running those stress tests? How thorough is stress coverage across the silicon? Moreover, does the probability of identifying a bug increase with higher stress? What about the case for lower stress? The answers to these questions can teach us how to create and improve an effective validation stress test plan. This paper describes a novel approach to extracting the stress map from a stress tool, applying a stress map to correlate with a stress-induced failure (bug), and assessing stress coverage across the entire validation test plan. It also discusses how the current validation stress test plan can be improved using lessons from previous stress-induced failure studies.
Event Type
Work-in-Progress Poster
TimeWednesday, June 265:00pm - 6:00pm PDT
LocationLevel 2 Lobby
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
IP
Security