Presentation
Hybrid Stochastic Computing of Linear Time O(N) and Its In-Memory Computing for High Performances
DescriptionSC reduces the complexity of arithmetic circuits but brings extra conversion cost and time complexity of O(2^N), which leads to a much lower efficiency than binary. This paper proposes a linear-time-complexity, O(N), and conversion-free hybrid stochastic computing (HSC). Moreover, a hybrid stochastic computing in-memory method is proposed, mapping multiplication and addition of HSC into memory's enable and addressing circuit. Thus, any original memory can realize HSC operation without additional circuits. The experiment shows that FPGA-based block memory (BRAM) operating matrix multiplication reaches 1.152 TOPS and 17.2 TOPS/W·bit. Each 18K-BRAM provides 18 GOPS performance (INT8) with 8.34 mW at 600 MHz.
Event Type
Work-in-Progress Poster
TimeWednesday, June 265:00pm - 6:00pm PDT
LocationLevel 2 Lobby
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