Presentation
Series-Parallel Hybrid SOT-MRAM Computing-in-Memory Macro with Multi-Method Modulation for High Area and Energy Efficiency
DescriptionMRAM is one of the most promising candidates for CIM. This paper proposes a series-parallel hybrid SOT-MRAM-CIM macro to solve the shortcomings of existing MRAM-CIM structures, like high energy cost and low operating frequency in traditional parallel or serial architecture. Additionally, we incorporate a multi-method modulation scheme, allowing for configurable precision (2/4/6/8-bit). We experimentally verified the performance of SOT-MRAM devices at 180-nm process node and design the macro at 28-nm node based on the test parameters of fabricated SOT devices. The simulation shows this macro can achieve energy efficiency of 23.7~29.6-Tops/W and computing frequency of 164.5-MHz/Bit at 8-bit precision.
Event Type
Research Manuscript
TimeTuesday, June 253:30pm - 3:45pm PDT
Location3003, 3rd Floor
Design
In-memory and Near-memory Computing Circuits