Presentation
Hardware-Accelerated Optimization of DSP-Based Equalizer in High-Speed ADC-Based Receivers
DescriptionAs four-level pulse-amplitude-modulation (PAM-4) signaling becomes widely adopted for high-speed wireline communication, achieving robust equalization is crucial due to reduced eye-opening compared to PAM-2. Utilizing analog-to-digital converters and digital signal processing with feed-forward equalizer (FFE) and decision-feedback equalizer (DFE), conventional equalizer adaptation may result in suboptimal bit-error-rate (BER) performance. This paper introduces an improved hill-climbing algorithm to obtain the optimal main tap position in FFE and the DFE tap coefficient. Implemented on an FPGA with a 12-tap FFE and 1-tap DFE, experimental results on a real channel model demonstrate superior BER performance compared to the conventional approaches.
Event Type
Work-in-Progress Poster
TimeTuesday, June 256:00pm - 7:00pm PDT
LocationLevel 2 Lobby
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
IP
Security