Presentation
Efficient Synaptic Delay Acceleration in Digital Event-Driven Neuromorphic Processors
DescriptionSynaptic delay parameterization of neural network models have
remained largely unexplored but recent literature has been show-
ing promising results, suggesting the delay parameterized models
are simpler, smaller, sparser, and more energy efficient than
similar performing non-delay parameterized
ones. We introduce Shared Circular Delay Queue (SCDQ), a novel
hardware structure for supporting synaptic delays on digital neuro-
morphic accelerators. Our analysis and hardware results show that
it scales better in terms of memory, than current commonly used
approaches, and is more amortizable to algorithm-hardware
co-optimizations, where in fact, memory scaling is modulated by
model sparsity and not merely network size.
remained largely unexplored but recent literature has been show-
ing promising results, suggesting the delay parameterized models
are simpler, smaller, sparser, and more energy efficient than
similar performing non-delay parameterized
ones. We introduce Shared Circular Delay Queue (SCDQ), a novel
hardware structure for supporting synaptic delays on digital neuro-
morphic accelerators. Our analysis and hardware results show that
it scales better in terms of memory, than current commonly used
approaches, and is more amortizable to algorithm-hardware
co-optimizations, where in fact, memory scaling is modulated by
model sparsity and not merely network size.
Event Type
Work-in-Progress Poster
TimeTuesday, June 256:00pm - 7:00pm PDT
LocationLevel 2 Lobby
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