Presentation
Integrated MAC-based Systolic Arrays: Design and Performance Evaluation
DescriptionIn the rapidly advancing landscape of computing, hardware accelerator designs are pivotal for satisfying high-performance and low-power demands. Systolic array (SA) architectures, tailored for general matrix multiplication (GEMM) operations, are ideal for image processing workloads. In this work, an integrated MAC (IMAC) factored SA is proposed. Unlike prior focus on standalone multipliers and adders, IMAC optimizes multiplier-and-accumulator (MAC) units. The new IMAC approach was introduced to three categories of Processing Elements (PE) that define SAs and were further evaluated against four state-of-the-art (SOTA) SA designs. IMAC-SA reported noteworthy advantages: a design footprint reduction of 17.30% to 26.40%, power savings from 5.46% to 15.85%, and a maximum critical path delay improvement of 9.47% over other SOTA designs.
Event Type
Work-in-Progress Poster
TimeTuesday, June 256:00pm - 7:00pm PDT
LocationLevel 2 Lobby
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