Presentation
ESFA: An Efficient Scalable FFT Accelerator Design Framework on Versal AI Engine
DescriptionThe fast Fourier transform (FFT) is widely used to convert a time-domain signal into its frequency-domain representation in various fields. Previous works have demonstrated efficient FFT implementation on various accelerators. The emergence of AI Engines (AIE) on AMD Xilinx's Versal ACAP brings the possibility of further improvement in computing efficiency. However, previous solutions have been restricted to a single-AIE manner, which limits the FFT size and neglects the potential of employing multiple AIEs. This paper proposes the ESFA framework, which can efficiently and automatically implement a scalable FFT on the Versal ACAP with multiple AIEs. The framework includes an analytical model to report the quality of results (QoRs) estimation for legal FFT partition modes, comprehensively covering the throughput-resource trade-off choices across the design space. In addition, an automatic code generator is developed in the framework to enable an agile implementation of the desired design. Our experiments on the VCK190 board show that we achieve 9,226 MS/s throughput on the 1K-point FFT with a data width of 32, which obtains up to 12.3x speedup compared with AMD Xilinx's library targeting AIE, meanwhile, 17.5x, 5.1x, and 10.1x speedup compared to the state-of-the-art designs based on ASIC, CGRA, FPGA.
Event Type
Work-in-Progress Poster
TimeTuesday, June 256:00pm - 7:00pm PDT
LocationLevel 2 Lobby
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
IP
Security