Presentation
Scaler-FFT: A Scalable FPGA-based FFT Accelerator via General Matrix Multiplication
DescriptionIn this paper, we propose Scaler-FFT, a scalable amd mix-precison FPGA-based FFT architecture via general matrix multiplication (GEMM). Specifically, Scaler-FFT is configurable and supports FFT calculations under different points and word lengths.
In addition, we customize a novel data management strategy. It allows us to read multiple sets of data from the RAM group at the same time in different stages of FFT, making it possible to accomplish FFT via GEMM for general architecture.
In order to maintain high accuracy, we also introduce a data shift strategy to prevent data overflow and increase the signal-to-quantization noise ratio.
In addition, we customize a novel data management strategy. It allows us to read multiple sets of data from the RAM group at the same time in different stages of FFT, making it possible to accomplish FFT via GEMM for general architecture.
In order to maintain high accuracy, we also introduce a data shift strategy to prevent data overflow and increase the signal-to-quantization noise ratio.
Event Type
Work-in-Progress Poster
TimeTuesday, June 256:00pm - 7:00pm PDT
LocationLevel 2 Lobby
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