Presentation
Unleashing the Potential of AQFP Logic Placement via Entanglement Entropy and Projection
DescriptionAdiabatic quantum-flux-parametron (AQFP) logic, known for its remarkable energy efficiency, has emerged as a prominent superconductor-based logic family, surpassing traditional rapid single flux quantum (RSFQ) logic. In AQFP circuits, each cell operates on AC power, serving as both a power supply and clock signal to drive data flow across clock phases. However, signal attenuation with increasing wire length may result in more potential data errors. To address this, rows of buffers are inserted as repeaters to ensure data synchronization and avoid wirelength violations. However, these inserted buffer rows in AQFP placement significantly amplifies power consumption and circuit delay.
To resolve these challenges, this paper propose an innovative and analytical method for AQFP placement. The proposed method aims to achieve minimizing the need for additional buffers. The framework incorporates two key features: (1) entanglement entropy for topology initialization and (2) projection for placement and buffering. These features offer advantages such as avoiding intensive computations, including fix-order Lagrangian optimization in large-scale scenarios, while significantly reducing the required number of buffer rows. Experimental results validate the efficiency of the proposed framework, demonstrating an outstanding 29% and 40% reduction in the amount of required buffers and time compared to the state-of-the-art method.
To resolve these challenges, this paper propose an innovative and analytical method for AQFP placement. The proposed method aims to achieve minimizing the need for additional buffers. The framework incorporates two key features: (1) entanglement entropy for topology initialization and (2) projection for placement and buffering. These features offer advantages such as avoiding intensive computations, including fix-order Lagrangian optimization in large-scale scenarios, while significantly reducing the required number of buffer rows. Experimental results validate the efficiency of the proposed framework, demonstrating an outstanding 29% and 40% reduction in the amount of required buffers and time compared to the state-of-the-art method.
Event Type
Research Manuscript
TimeThursday, June 271:45pm - 2:00pm PDT
Location3004, 3rd Floor
EDA
Physical Design and Verification