Session

DescriptionTake this journey with us through the amazing world of physical design and learn about novel algorithms to tame the challenges arising from the growing complexities in technology scaling and advanced packaging! Topics include faster and more accurate yield prediction, standard cell design co-optimization, package-level GPU-accelerated design rule checker, performance-improving placement-aware logic resynthesis and datapath-aware mixed-size placement approaches, advanced techniques for synthesizing cutting-edge CFET-based standard cells with much lower area and routing resources, and a highly efficient placement algorithm for significantly boosting performance of ultra-low power adiabatic quantum-flux parametron-based logic designs for high-performance computing applications.