Presentation
Quantifying the Energy Efficiency Benefits of Monolithic 3D Refreshless Embedded-DRAM
DescriptionFuture energy-efficient computing systems require new memory designs to overcome the challenges of transistor scaling. This paper presents a design space exploration methodology for rapid analysis of heterogeneous monolithic 3D integration for on-chip dynamic random-access memory. We develop a model for memory analysis validated with tape-out measurements and profile software applications with different memory access patterns. Using a system comprising silicon, carbon-nanotube and indium-gallium-zinc-oxide field effect transistors, we show that such designs can achieve 2.8x and 291x improvements in energy-delay-product in addition to 50% and 33% reductions in bit-cell area compared to silicon-based 6T-SRAM and 3T-eDRAM for embedded applications.
Event Type
Work-in-Progress Poster
TimeTuesday, June 256:00pm - 7:00pm PDT
LocationLevel 2 Lobby
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
IP
Security