Presentation
PPA-Relevant Clustering-Driven Placement for Large-Scale VLSI Designs
DescriptionToday's place-and-route (P&R) flows are increasingly challenged by complexity and scale of modern designs. Often, heuristics must trade off between turnaround time and quality of PPA outcomes. This paper presents a clustered placement methodology that improves both turnaround time and final-routed solution quality. Our PPA-aware clustering considers timing, power and logical hierarchy during netlist clustering, effectively reducing problem size and accelerating global placement runtime while improving post-route PPA metrics. Additionally, our machine learning (ML)-accelerated virtualized P&R (V-P&R) methodology predicts the best cluster shapes (i.e., aspect ratios and utilizations) to use in P&R of the clustered netlist. With the open-source OpenROAD tool, our methods achieve up to 47% (average: 36%) global placement runtime improvement with similar half-perimeter wirelength (HPWL) and 90% (29%) improvement in post-route total negative slack (TNS). With the commercial Cadence Innovus tool, our methods achieve up to 1.68% (0.00%) improvement in power and 94% (44%) improvement in TNS.
Event Type
Research Manuscript
TimeThursday, June 272:30pm - 2:45pm PDT
Location3004, 3rd Floor
EDA
Physical Design and Verification