Presentation
A General Purpose IMC Architecture with ADC-Awared Neural Networks
DescriptionIn analog or mixed-signal in-memory computing (IMC) applications, the focus is typically on the bit cell, particularly during the inference period. However, for transmitting multiplication-and-accumulation (MAC) results to subsequent layers, IMC macros must convert analog signals into digital domain using analog-to-digital converters (ADCs), often the most power and area-intensive components in IMC systems. Addressing this, we present an efficient training/inferencing algorithm tailored for specific IMC applications, introducing an ADC-less IMC macro design suitable for practical memory systems. This novel architecture eliminates the need for power-intensive ADCs, opting for reconfigurable conventional memory structures with sense amplifiers, like DRAM or SRAM arrays. This study introduces an algorithm that integrates sense amplifiers into both the training and inference processes without extra hardware additives.
Event Type
Work-in-Progress Poster
TimeTuesday, June 256:00pm - 7:00pm PDT
LocationLevel 2 Lobby
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