Presentation
Revisiting Automatic Pipelining: Gate-level Forwarding and Speculation
DescriptionThe key to pipeline throughput optimization is to resolve data hazards caused by read-after-write (RAW) dependencies, which are traditionally tackled by forwarding and speculation to avoid pipeline stalls. However, existing approaches are conducted based on high-level dataflow analysis, with potential loss of optimization opportunities for lack of analysis of the netlist structures.
We propose an efficient method to resolve RAW dependencies with low-level netlist analysis by gate-level forwarding and speculation. With a greedy search method to detect and resolve short-delay gate-level signal paths for forwarding and an approximate circuit synthesis method with formal verification for gate-level speculation, the method efficiently utilizes the gate-level information to further improve pipeline throughput. We conduct experiments on the widely-used ISCAS/EPFL benchmark circuits and a large-scale RISC-V CPU. Experimental results show that our approach can increase the pipeline throughput. More importantly, our approach can find better designs than human experts.
We propose an efficient method to resolve RAW dependencies with low-level netlist analysis by gate-level forwarding and speculation. With a greedy search method to detect and resolve short-delay gate-level signal paths for forwarding and an approximate circuit synthesis method with formal verification for gate-level speculation, the method efficiently utilizes the gate-level information to further improve pipeline throughput. We conduct experiments on the widely-used ISCAS/EPFL benchmark circuits and a large-scale RISC-V CPU. Experimental results show that our approach can increase the pipeline throughput. More importantly, our approach can find better designs than human experts.
Event Type
Research Manuscript
TimeTuesday, June 252:15pm - 2:30pm PDT
Location3004, 3rd Floor
EDA
RTL/Logic Level and High-level Synthesis