Session

DescriptionThis session includes six advanced logic synthesis works in addressing fundamental challenges of runtime efficiency and handling complex optimization objectives. The first two papers focus on high-performance parallel DAG-aware logic synthesis, exploring both GPU and CPU parallelism. The third and fourth presentations introduce and merge synthesis techniques in circuit-level architecture optimization, showcasing parallel prefix circuit design and pipelining. The fifth and sixth papers present novel formal methods, including Satisfiability and e-graphs, based on logic synthesis approaches to tackle complex optimization objectives in the conventional logic synthesis process.