Presentation
Learned Index Acceleration with FPGAs: A SMART Approach
DescriptionIndexes such as B-trees and hash tables, in database systems are used for fast retrieval of data. These are created on columns of a table and serve as a pointer in order to map a key to the position of a record on a table. In recent years, much research has been conducted on the faster index lookup. "Learned indexes" is one such area of research. These index models have achieved enormous performance improvements. However, query performance with learned indexes is restricted by CPU architecture.
FPGAs, on the other hand, offer a suitable alternative, by providing programmability. In this paper, we propose a new methodology that takes into consideration the advantages of both the learned index and FPGAs. We refer to this methodology as the Selective Mathematical operation AcceleRaTion (SMART) approach with an FPGA for the end-to-end acceleration of learned indexes. Being a hybrid between a CPU approach and an FPGA approach, the SMART model of index acceleration achieves FPGA-like performance while maintaining the data structure storage on the CPU.
With our SMART approach, the radix spline learned index was accelerated using the single FPGA and without any off-chip memory resources. The resulting index, called SMART-RS, achieves an overall speedup of 5.5× as compared to a CPU-based RS index on the SOSD benchmark datasets.
FPGAs, on the other hand, offer a suitable alternative, by providing programmability. In this paper, we propose a new methodology that takes into consideration the advantages of both the learned index and FPGAs. We refer to this methodology as the Selective Mathematical operation AcceleRaTion (SMART) approach with an FPGA for the end-to-end acceleration of learned indexes. Being a hybrid between a CPU approach and an FPGA approach, the SMART model of index acceleration achieves FPGA-like performance while maintaining the data structure storage on the CPU.
With our SMART approach, the radix spline learned index was accelerated using the single FPGA and without any off-chip memory resources. The resulting index, called SMART-RS, achieves an overall speedup of 5.5× as compared to a CPU-based RS index on the SOSD benchmark datasets.
Event Type
Work-in-Progress Poster
TimeTuesday, June 256:00pm - 7:00pm PDT
LocationLevel 2 Lobby
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