Presentation
A Parallel-trial Double-update Annealing Algorithm for Enabling Highly-effective State Transition on Annealing Processors
DescriptionAnnealing processors have attracted attention as domain-specific computers to solve combinatorial optimization problems (COPs) efficiently. Furthermore, their performance can be enhanced by the merge method that enables updating multi-variables simultaneously. However, directly implementing the merge method on an annealing processor requires large-scale computational and memory resources.
In this paper, we propose a parallel-trial double-update annealing (PDA) algorithm that integrates the merge method into the annealing computation flow. Also, we can realize its processor by a minor extension to the existing near-memory architecture. Simulation results for several COPs demonstrate that PDA can find higher quality solutions than the conventional annealing algorithm.
In this paper, we propose a parallel-trial double-update annealing (PDA) algorithm that integrates the merge method into the annealing computation flow. Also, we can realize its processor by a minor extension to the existing near-memory architecture. Simulation results for several COPs demonstrate that PDA can find higher quality solutions than the conventional annealing algorithm.
Event Type
Work-in-Progress Poster
TimeTuesday, June 256:00pm - 7:00pm PDT
LocationLevel 2 Lobby
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