Presentation
Concurrent Detailed Routing with Pin Pattern Re-generation for Ultimate Pin Access Optimization
DescriptionPin access has become one of the most significant challenges in large-scale full-chip routing due to the continuous reduction in feature sizes and the increasing complexity of designs. The conventional standard cell layout synthesis approaches usually optimize pin accessibility by maximizing pin lengths and access points. However, these pre-determined pin patterns greatly occupy routing resources and may contrarily degrade routability. To address this problem, this paper proposes the first work of concurrent detailed routing with pin pattern re-generation to achieve ultimate pin access optimization. A pseudo-pin extraction and routing technique is proposed that can secure one access point for each input/output pin while allowing the remaining access points to be routable by other nets. The experimental results demonstrate that the proposed method can resolve 89% of local regions that are unroutable with original layout patterns without compromising power and timing performances.
Event Type
Research Manuscript
TimeWednesday, June 265:15pm - 5:30pm PDT
Location3010, 3rd Floor
EDA
Physical Design and Verification