Session
On the Right Path: Navigating the Maze of Routing and Clock Tree Synthesis!
DescriptionYou have made it all the way here! So come hither and learn about the latest advanced algorithms to address the increasingly complex signal and data routing challenges! These include a novel reinforcement learning-based approach for obstacle-aware Steiner trees, an insightful pin-access co-optimization framework through on-the-fly standard cell pin layout regeneration, top-level design routing, minimal area length matching for PCB routing, a priori resource allocation-based router, a latency/load capacitance-centric approach for clock tree synthesis, and a GNN-assisted back-side clock routing algorithm.
Event TypeResearch Manuscript
TimeWednesday, June 263:30pm - 5:30pm PDT
Location3010, 3rd Floor
EDA
Physical Design and Verification
Presentations
3:30pm - 3:45pm PDT | Obstacle-Aware Length-Matching Routing for Any-Direction Traces in Printed Circuit Board | |
3:45pm - 4:00pm PDT | Toward Controllable Hierarchical Clock Tree Synthesis with Skew-Latency-Load Tree | |
4:00pm - 4:15pm PDT | Net Resource Allocation: A Desirable Initial Routing Step | |
4:15pm - 4:30pm PDT | Arbitrary-size Multi-layer OARSMT RL Router Trained with Combinatorial Monte-Carlo Tree Search | |
4:30pm - 4:45pm PDT | GNN-assisted Back-side Clock Routing Methodology for Advance Technologies | |
4:45pm - 5:00pm PDT | DGR: Differentiable Global Router | |
5:00pm - 5:15pm PDT | Top-Level Routing for Multiply-Instantiated Blocks with Topology Hashing | |
5:15pm - 5:30pm PDT | Concurrent Detailed Routing with Pin Pattern Re-generation for Ultimate Pin Access Optimization |