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Research Manuscript: On the Right Path: Navigating the Maze of Routing and Clock Tree Synthesis!
DescriptionYou have made it all the way here! So come hither and learn about the latest advanced algorithms to address the increasingly complex signal and data routing challenges! These include a novel reinforcement learning-based approach for obstacle-aware Steiner trees, an insightful pin-access co-optimization framework through on-the-fly standard cell pin layout regeneration, top-level design routing, minimal area length matching for PCB routing, a priori resource allocation-based router, a latency/load capacitance-centric approach for clock tree synthesis, and a GNN-assisted back-side clock routing algorithm.
Event TypeResearch Manuscript
TimeWednesday, June 263:30pm - 5:30pm PDT
Location3010, 3rd Floor
Topics
EDA
Keywords
Physical Design and Verification