Presentation
mROB: Multi-Level ReOrder Buffer Design with Reduced Area and Power
DescriptionRe-Order Buffer (ROB) is a fundamental component in modern microprocessor designs. A novel design is proposed to significantly reduce the area and dynamic power of a conventional ROB design without performance loss. A novel hardware structure removes redundancies existing in the original ROB entries by storing common information shared by many such entries separately. Cycle-accurate simulation results show that the area and power are reduced by 47% and 39% respectively in a CPU configuration modelled after the Intel Skylake processor. A design methodology is proposed for the
novel design considering a trade-off between performance and power/area with a quantitative approach.
novel design considering a trade-off between performance and power/area with a quantitative approach.
Event Type
Work-in-Progress Poster
TimeWednesday, June 265:00pm - 6:00pm PDT
LocationLevel 2 Lobby
AI
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Embedded Systems
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