Presentation
SPHINCSLET - A Lightweight Implementation of SPHINCS+
DescriptionThis work presents the first, fully standard-complaint and lightweight hardware implementation of the SLH-DSA, formerly known as SPHINCS+, post-quantum digital signature scheme. The design is parameterizable across different security levels and different performance targets. The area footprint on a Xilinx Artix 7 FPGA of the presented hardware implementation based on the configurable parameters lies in the range of 3K to 14K LUTs, becoming currently the smallest SPHINCS+ implementations in the literature. The present implementation of SLH-DSA is suitable for lightweight and area-constrained IoT devices, for example, as IoT and other devices migrate to post-quantum~cryptography.
Event Type
Work-in-Progress Poster
TimeTuesday, June 256:00pm - 7:00pm PDT
LocationLevel 2 Lobby
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
IP
Security