Presentation
Geneva: A Dynamic Confluence of Speculative Execution and In-Order Commitment Windows
DescriptionModern out-of-order processors are increasingly expanding resources such as reorder buffer (ROB) and instruction queue (IQ) for memory-level parallelism (MLP). While this expansion effectively addresses the memory wall challenge, it also incurs notable cost and energy trade-offs. To tackle this, we propose Geneva, a microarchitecture that improves performance and energy efficiency. Geneva reallocates a portion of the ROB to serve as a dynamic queue (DQ), used as the ROB, IQ, or both depending on operational needs. Geneva saves energy by 15.6% and improves performance by 2.6% compared to the out-of-order core baseline.
Event Type
Research Manuscript
TimeWednesday, June 265:15pm - 5:30pm PDT
Location3003, 3rd Floor
Design
SoC, Heterogeneous, and Reconfigurable Architectures