Session

DescriptionHardware accelerators are integral in modern computing systems to deliver the required performance-per-Watt efficiency by exploiting fine-grained spatial concurrency. Programmable and reconfigurable accelerators are important in extending hardware acceleration efficiency to a still larger and more diverse share of computing tasks. This session showcases novel applications of Field Programmable Gate Arrays, GPUs, and chiplets to accelerate new computing problems. This session also presents new advances in EDA algorithms to improve application mapping to Coarse-Grained Reconfigurable Architectures. The final paper explores reconfiguration within a von Neumann processor datapath to efficiently specialize to changing applications.