Presentation
TACPlace: Ultrafast Thermal-Aware Chiplet Placement under Multi-Power Mode Using Feasibility Seeking
Description2.5D integrated technology offers advanced design capabilities with enhanced functionality and higher performance. However, the increasing power density of modern chiplets poses significant challenges to inter-chiplet placement, considering multiple constraints introduced by routing, thermal management, and power distribution.
We propose TACPlace, a hyper-efficient thermal-aware placement framework that jointly explores these complex constraints within low whitespace. As the first feasibility-seeking 2.5D placer, TACPlace incorporates both the ultrafast and accurate thermal simulation based on Green's function and the routing optimization, for thermal-\&wirelength-aware perturbations. TACPlace also fills the void of supporting multi-power mode, \ie considering different working modes of the 2.5D system.
Experiments over real-world 2.5D systems demonstrate a speedup of placement from hours to seconds, an average 23.9\% decreased wirelength, and up to 3.4\textcelsius{} reduction in peak temperature in contrast with the state of the art. Furthermore, TACPlace tailored for multiple workloads achieves an averaged 6.2\textcelsius{} lower peak temperature than single-power mode.
We propose TACPlace, a hyper-efficient thermal-aware placement framework that jointly explores these complex constraints within low whitespace. As the first feasibility-seeking 2.5D placer, TACPlace incorporates both the ultrafast and accurate thermal simulation based on Green's function and the routing optimization, for thermal-\&wirelength-aware perturbations. TACPlace also fills the void of supporting multi-power mode, \ie considering different working modes of the 2.5D system.
Experiments over real-world 2.5D systems demonstrate a speedup of placement from hours to seconds, an average 23.9\% decreased wirelength, and up to 3.4\textcelsius{} reduction in peak temperature in contrast with the state of the art. Furthermore, TACPlace tailored for multiple workloads achieves an averaged 6.2\textcelsius{} lower peak temperature than single-power mode.
Event Type
Work-in-Progress Poster
TimeWednesday, June 265:00pm - 6:00pm PDT
LocationLevel 2 Lobby
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
IP
Security