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Organization

Peking University
Contributors
Renze Chen
Zhiyuan Chen
Tuo Dai
Zijian Ding
Yanchi Dong
Yiheng Du
Yufan Du
Xiaohan Gao
Zizheng Guo
Qianqian Huang
Ru Huang
Tianyu Jia
Yifan Jia
Xun Jiang
Yiqi Jing
Zichen Kong
Guoxiang Li
Keyi Li
Meng Li
Mingxuan Li
Tongyang Li
Xingchen Li
Xiuhong Li
LING LIANG
Yun (Eric) Liang
Chenqi Lin
Yibo Lin
Haiyang Liu
Kecheng Liu
Guojie Luo
Jin Luo
Yufei Ma
Qingni Shen
Bizhao Shi
Jiahao Song
Guangyu Sun
Yiyang Sun
Xiyuan Tang
Jiarui Wang
QianKun Wang
Runsheng Wang
Wentao Wang
Yuan Wang
Xinming Wei
Xuechao Wei
Meng Wu
Meng Wu
Zhonghai Wu
Tianshi Xu
Weikai Xu
Chenhao Xue
Bonan Yan
Shengen Yan
Chao Yang
Rui Yang
Zebin Yang
Zhi Yang
Zhuoxi Yang
Le Ye
Shan Yu
Haoyi Zhang
Jiaxi Zhang
Xin Zhang
Yuxiang Zhao
Qilin Zheng
Size Zheng
Qinzhe Zhi
Jiaqi Zhou
Zhe Zhou
Sunan Zou
Session Chairs
Yibo Lin
Presentations
Research Manuscript
A High-Throughput Private Inference Engine Based on 3D Stacked Memory
Security
Hardware Security: Primitives, Architecture, Design & Test
Research Manuscript
A Holistic Functionalization Approach to Optimizing Imperative Tensor Programs in Deep Learning
AI
AI/ML Application and Infrastructure
Research Manuscript
A Software-Hardware Co-design Solution for 3D Inner Structure Reconstruction
AI
Design
AI/ML Architecture Design
Research Manuscript
Accelerating Regular Path Queries over Graph Database with Processing-in-Memory
Design
In-memory and Near-memory Computing Circuits
Research Manuscript
AIG-CIM: A Scalable Chiplet Module with Tri-Gear Heterogeneous Compute-in-Memory for Diffusion Acceleration
Design
In-memory and Near-memory Computing Architectures, Applications and Systems
Research Manuscript
Alchemist: A Unified Accelerator Architecture for Cross-Scheme Fully Homomorphic Encryption
Security
Hardware Security: Primitives, Architecture, Design & Test
Work-in-Progress Poster
An Effective Timing Driven Placement with Accurate Differentiable Timing Approximation Integration
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
IP
Security
Research Manuscript
An In-Memory Computing Accelerator with Reconfigurable Dataflow for Multi-Scale Vision Transformer with Hybrid Topology
Design
In-memory and Near-memory Computing Architectures, Applications and Systems
Research Manuscript
Combining Parameterized Pulses and Contextual Subspace for More Practical VQE
Design
Quantum Computing
Research Manuscript
Compact and Efficient CAM Architecture through Combinatorial Encoding and Self-Terminating Searching for In-Memory-Searching Accelerator
Design
In-memory and Near-memory Computing Circuits
Work-in-Progress Poster
DATIS: DRAM Architecture and Technology Integrated Simulation
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
IP
Security
Research Manuscript
EasyACIM: An End-to-End Automated Analog CIM with Synthesizable Architecture and Agile Design Space Exploration
Design
In-memory and Near-memory Computing Circuits
Research Manuscript
FastQuery: Communication-efficient Embedding Table Query for Private LLMs inference
AI
Security
AI/ML Security/Privacy
Research Manuscript
G-kway: Multilevel GPU-Accelerated k-way Graph Partitioner
Design
SoC, Heterogeneous, and Reconfigurable Architectures
Research Manuscript
G2PM: Performance Modeling for ACAP Architecture with Dual-Tiered Graph Representation Learning
AI
AI/ML Application and Infrastructure
Research Manuscript
Graph Neural Networks Automated Design and Deployment on Device-Edge Co-Inference Systems
AI
AI/ML Algorithms
Research Manuscript
Lesyn: Placement-aware Logic Resynthesis for Non-Integer Multiple-Cell-Height Designs
EDA
Physical Design and Verification
Research Manuscript
MoteNN: Memory Optimization via Fine-grained Scheduling for Deep Neural Networks on Tiny Devices
AI
Design
AI/ML System and Platform Design
Research Manuscript
Oltron: Algorithm-Hardware Co-design for Outlier-Aware Quantization of LLMs with Inter-/Intra-Layer Adaptation
AI
Design
AI/ML Architecture Design
Research Manuscript
PONO: Power Optimization with Near Optimal SMT-based Sub-circuit Generation
EDA
RTL/Logic Level and High-level Synthesis
Research Manuscript
PowPrediCT: Cross-Stage Power Prediction with Circuit-Transformation-Aware Learning
EDA
Timing and Power Analysis and Optimization
Research Manuscript
PT-Map: Efficient Program Transformation Optimization for CGRA Mapping
Design
SoC, Heterogeneous, and Reconfigurable Architectures
Research Manuscript
PVTSizing: A TuRBO-RL-Based Batch-Sampling Optimization Framework for PVT-Robust Analog Circuit Synthesis
EDA
Analog CAD, Simulation, Verification and Test
Work-in-Progress Poster
QPulse: Ansatz Design Analysis and Advantages of Parameterized Quantum Pulses
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
IP
Security
Research Manuscript
SPARK: An Efficient Hybrid Acceleration Architecture with Run-Time Sparsity-Aware Scheduling for TinyML Learning
Design
Design of Cyber-physical Systems and IoT
Research Manuscript
SpREM: Exploiting Hamming Sparsity for Fast Quantum Readout Error Mitigation
Design
Quantum Computing
Work-in-Progress Poster
TACPlace: Ultrafast Thermal-Aware Chiplet Placement under Multi-Power Mode Using Feasibility Seeking
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
IP
Security
Research Manuscript
ThermalScope: A Practical Interrupt Side Channel Attack Based on Thermal Event Interrupts
Security
Hardware Security: Attack and Defense
Research Manuscript
Top-Level Routing for Multiply-Instantiated Blocks with Topology Hashing
EDA
Physical Design and Verification
Research Manuscript
Towards Efficient SRAM-PIM Architecture Design by Exploiting Unstructured Bit-Level Sparsity
Design
In-memory and Near-memory Computing Architectures, Applications and Systems
Sessions
Research Manuscript
Racing Against Time: Innovations in Timing
EDA
Timing and Power Analysis and Optimization