Presentation
Optimal Transistor Folding and Placement for Synthesizing Standard Cells of Complementary FET Technology
DescriptionAs the VLSI technology continues to scale beyond 5nm, a strong demand on the continuing layout reduction of standard cells is required. However, the standard cells with conventional FinFET or nanosheet-FET structure are becoming much hard to meet this requirement due to the lateral P-FET and N-FET separation. It has been widely accepted that Complementary-FET (CFET) is a promising technology, which stacks P-FET on N-FET or vice versa, to achieve this objective. In comparison with synthesizing the conventional FET based standard cells, two prominent optimization tasks in CFET based multi-row cell synthesis that significantly affect the cell quality, in terms of area and routability, are (1) determining transistor folding shapes and (2) determining placement order of transistors with fully secured vertical i.e., z-directional routing space on the stacked FETs as well as buried power rail (BPR). In this work, we propose an optimal solution to the combined problem of tasks 1 and 2. Precisely, we develop a search tree-based area-optimal method of transistor folding and placement, in which we accelerate the cost computation of partial solutions by formulating it into dynamic programming while performing a strict feasibility checking of securing in-cell vertical routing space of partial solutions by formulating and solving it into an instance of network flow problem. Through experiment with benchmark circuits, it is shown that the CFET cells produced by our cell synthesizer are 14% smaller in size on average even with 31% shorter total metal length and 52% less use of metal2 for in-cell routing over the cells produced by the recent state-of-the-art CFET cell generator.
Event Type
Research Manuscript
TimeThursday, June 272:15pm - 2:30pm PDT
Location3004, 3rd Floor
EDA
Physical Design and Verification