Presentation
Methodology of configurable memory conflict-free Number Theoretic Transform accelerator for FPGA platform
DescriptionThe Number Theoretic Transform (NTT) has proven effective in enhancing polynomial multiplication efficiency for fully homomorphic encryption(FHE), yet lacks a universal methodology for generating NTT accelerators. In this paper, we propose a methodology for the NTT accelerator that accommodates polynomials of arbitrary degrees and moduli, achieving a balance between area and performance by adjusting the number of Processing Elements (PEs). Our design employs the Residue Number System (RNS) for modulus decomposition to enhance hardware resource utilization. In addition, we introduce a data movement strategy that eliminates bit-reversal operations, addresses memory conflicts, and reduces the clock cycle. Finally, we develop a configurable PE capable of adapting its data path, resulting in a universal architecture. The evaluation demonstrates that our design outperforms the existing work by 40% improvement in area-time product on average and up to 21.7× improvement in processing speed
Event Type
Work-in-Progress Poster
TimeTuesday, June 256:00pm - 7:00pm PDT
LocationLevel 2 Lobby
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
IP
Security