Presentation
Performance-driven Analog Routing via Heterogeneous 3DGNN and Potential Relaxation
DescriptionAnalog routing is crucial for performance optimization in analog circuit design, but conventionally takes significant development time and requires design expertise. Recent research has attempted to use machine learning (ML) to generate guidance to preserve circuit performance after analog routing. These methods face challenges such as expensive data acquisition and biased guidance. In this paper, we introduce AnalogFold, a new paradigm of analog routing leveraging ML-enabled performance-oriented routing guidance. Our approach learns performance-driven routing guidance and uses it to help automatic routers for performance-driven routing optimization. We propose to use a 3DGNN that incorporates cost-aware distance to make accurate predictions on post-layout performance. A pool-assisted potential relaxation process derives the effective routing guidance. The experimental results on multiple benchmarks under the TSMC 40nm technology node demonstrate the superiority of the proposed framework compared to the cutting-edge works.
Event Type
Research Manuscript
TimeWednesday, June 2611:45am - 12:00pm PDT
Location3010, 3rd Floor
EDA
Analog CAD, Simulation, Verification and Test