Presentation
A Cache/Algorithm Co-design for Parallel Real-Time Systems with Data Dependency on Multi/Many-core System-on-Chips
SessionGetting Real in Real-Time
DescriptionParallel real-time systems often rely on the shared cache for dependent data transmissions across cores. Conventional shared cache and their management techniques suffer from intensive contention and are markedly inflexible, leading to significant transmission latency of shared data. In this paper, we provide a Virtual Indexed Physical Tagged, Selectively-Inclusive Non-Exclusive L1.5 Cache, offering way-level control and versatile sharing capabilities. Focusing on a common-seen parallel task model, the Directed Acyclic Graph (DAG), we construct a novel scheduling method that exploits the L1.5 Cache to reduce data transmission latency, achieving improved timing performance. As a systematical solution, we build a real system, from the SoC and ISA to the drivers and the programming model. Experiments show that the proposed solution significantly improves the real-time performance of DAG tasks with negligible hardware overhead.
Event Type
Research Manuscript
TimeTuesday, June 2510:45am - 11:00am PDT
Location3012, 3rd Floor
Embedded Systems
Time-Critical and Fault-Tolerant System Design