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Research Manuscript: Getting Real in Real-Time
DescriptionMultimodal transformers get real-time performance boost using PIM-GPU collaboration. What's more, DNN inference tasks can be modeled as sporadic non-preemptive gang tasks. For parallel real-time applications on SoCs, an extra cache layer shared by a cluster improves latency. To protect CNNs, algorithm-based comprehensive fault tolerance can be used to "maintain sanity". Analysis of NN layers reveals that faults transitioning from 0 to 1 significantly impact classification outcomes. From the networking side, a real-time TSN end station design enables ultra-low latency and nanosecond-level transmission accuracy.
Event TypeResearch Manuscript
TimeTuesday, June 2510:30am - 12:00pm PDT
Location3012, 3rd Floor
Topics
Embedded Systems
Keywords
Time-Critical and Fault-Tolerant System Design