Session

DescriptionThis session includes eight papers on the latest development of hardware security primitives for security and privacy. The first paper describes a novel circuit architecture for true random number generation (TRNG). The second paper proposes an authenticated partial encryption protocol to enable secure testing of system in package (SiP). The third paper presents an architecture for the processing of multi-scalar multiplication, a fundamental cryptographic operation. Then we have a group of papers focusing on the acceleration of fully homomorphic encryption (FHE) based on the low-level operator Meta-OP (paper No. 4); a scalable memory mapping algorithm and a flexible no-stall hardware/software pipeline (paper No. 5); specialized units for the pipelined processing of FHE operations (paper No. 6); and 3D stacked memory (paper No. 7). The session concludes with the design and fabrication of a subthreshold SRAM PUF with zero bit error rate across all voltage/temperature corners.