Session

DescriptionThis session highlights advancements in layout optimization, TCAD, accurate yield estimation, and soft error estimation techniques, together shaping the future of semiconductor design and reliability. The session explores topics like natural language assisted layout customization, TCAD simulation enhancement via advanced physics-informed neural networks, efficient Bayesian models for yield optimization, rare circuit failure analysis using normalizing flow, novel machine learning approaches to SEM defect segmentation, and how soft error impact estimation is handled in edge AI SoCs, with insights into measured vs., simulated data.