Presenter
Sainarayanan Suryanarayanan
Biography
Sai has around 18+ years of experience in semiconductor industry. Currently he works for Marvell as a CAD Director, driving the India Center CAD & Methodology team. He spearheads the Static Timing Analysis (STA) and Power Integrity CAD flows for world-wide Marvell. Prior to joining Marvell he worked at ARM, AMD and Conexant. Sai has worked on various aspects of digital implementation, flow, methodology & circuit simulation
Sai has close to 25+ papers in various IEEE conferences & EDA conferences like DAC,GLVLSI,ISQED,ISVLSI,TENCON,VLSID etc. in the areas of low-power, power integrity and variability and also has a US patent. Some of his papers are cited in various books and patents. He holds a M.S (by Research) degree from IIIT-Hyderabad and B.E(ECE) from Madras University
Sai has close to 25+ papers in various IEEE conferences & EDA conferences like DAC,GLVLSI,ISQED,ISVLSI,TENCON,VLSID etc. in the areas of low-power, power integrity and variability and also has a US patent. Some of his papers are cited in various books and patents. He holds a M.S (by Research) degree from IIIT-Hyderabad and B.E(ECE) from Madras University
Presentations
Back-End Design
Back-End Design
Design
Engineering Tracks
Back-End Design
Back-End Design
Design
Engineering Tracks