Presentation
Timing Robustness: A Way forward for analyzing timing-voltage sensitive paths for accounting IR-Drop Variations
DescriptionWith increasing grid resistance, modelling the impact of voltage drop on instances has been a focus of research to improve timing robustness or yield. Furthermore, as technology node shrinks, RC constant is dominated by Resistance, with R increasing 10x from 28nm-7nm, and cell delays are non-linear with IR drop, accounting for higher delay variations at below nominal voltage domain.
Traditionally and still mostly as well, designers use derating techniques to account for the IR drop. The limitation of this approach is that it is a flat OCV factor and sometimes we penalize paths which are not as prone to voltage sensitivity causing excessive pessimism and on the other hand could mask potential real violations. These issues paved the way towards IR aware STA wherein voltage drop obtained from IR tools are back-annotated onto the timing engine. This method is robust but still depends on the coverage done using vectorless dynamic analysis. In order to perform analysis on timing critical and voltage sensitive path we need to have both the timer and the power-grid solver integrated so that we could perform more voltage sensitive focused critical timing path analysis. This methodology can serve as an augmentation to regular signoff and can potentially unravel timing voltage sensitive instances which are missed by traditional methods leading to more robustness and silicon success. In this paper we will be presenting a case study on evolution and adoption for accounting IR-Drop variations, results and current limitations.
• Timing-Power Integrated Flow for concurrent Timing and Voltage-Drop analysis: Paper will walk
through the STA-PI integration flow with different STA and IR analysis corners under a common
cockpit (SLOW corner STA and TYP corner IR) and evaluates the benefits of timing-aware IR and
IR aware timing analysis
• Detailed analysis on Timing/IR critical Block: Paper presents the quantitative analysis done on
timing sensitive paths with annotated EIV values for voltage drop on timing instances and its
comparison with the traditional Flat Voltage derates and IR-aware STA flow
• Resource and runtime evaluation for Large Designs: With analysis done on a 100M instance
block, paper will focus on the resource/runtime trade-offs with PPA and robustness gains
• Timing ECOs with EIV annotation and timing fixes: Timing ECOs with EIV annotated timing paths
with focus on fixing Voltage-Sensitive timing critical paths
• Potential missed violations: Paper will also focus on timing paths which were not violating with Flat
voltage derates but seen as potential violators with the discussed flow
Traditionally and still mostly as well, designers use derating techniques to account for the IR drop. The limitation of this approach is that it is a flat OCV factor and sometimes we penalize paths which are not as prone to voltage sensitivity causing excessive pessimism and on the other hand could mask potential real violations. These issues paved the way towards IR aware STA wherein voltage drop obtained from IR tools are back-annotated onto the timing engine. This method is robust but still depends on the coverage done using vectorless dynamic analysis. In order to perform analysis on timing critical and voltage sensitive path we need to have both the timer and the power-grid solver integrated so that we could perform more voltage sensitive focused critical timing path analysis. This methodology can serve as an augmentation to regular signoff and can potentially unravel timing voltage sensitive instances which are missed by traditional methods leading to more robustness and silicon success. In this paper we will be presenting a case study on evolution and adoption for accounting IR-Drop variations, results and current limitations.
• Timing-Power Integrated Flow for concurrent Timing and Voltage-Drop analysis: Paper will walk
through the STA-PI integration flow with different STA and IR analysis corners under a common
cockpit (SLOW corner STA and TYP corner IR) and evaluates the benefits of timing-aware IR and
IR aware timing analysis
• Detailed analysis on Timing/IR critical Block: Paper presents the quantitative analysis done on
timing sensitive paths with annotated EIV values for voltage drop on timing instances and its
comparison with the traditional Flat Voltage derates and IR-aware STA flow
• Resource and runtime evaluation for Large Designs: With analysis done on a 100M instance
block, paper will focus on the resource/runtime trade-offs with PPA and robustness gains
• Timing ECOs with EIV annotation and timing fixes: Timing ECOs with EIV annotated timing paths
with focus on fixing Voltage-Sensitive timing critical paths
• Potential missed violations: Paper will also focus on timing paths which were not violating with Flat
voltage derates but seen as potential violators with the discussed flow
Event Type
Back-End Design
TimeTuesday, June 2511:06am - 11:24am PDT
Location2008, 2nd Floor
Back-End Design
Design
Engineering Tracks