Presentation
An effective Hierarchical STA solution for closing Large SoC Design
DescriptionFull-Chip STA is a mandatory step for Design closure cycle. With extensive market requirements for high computational workloads, design sizes are growing along with the ask for performance and area. With Chips getting fabricated on shrinking technology nodes, this further tightens the impact window on design accuracy and pessimism. To cater for the mentioned needs, designs are highly modularized at architecture level, but when it comes to STA, performing a Full-Chip Flat STA is the only option for computing exact design performance.
Flat STA on big designs comes with a high cost of runtime and memory requirements, which makes flat STA performed at final design closure stage as the optimal situation. Hence, there are methodologies to perform faster STA, for e.g., distributed chip timing analysis and Hierarchical Timing analysis, which can save on runtime & memory requirements, but could show an impact on accuracy.
For flexibility in STA methodologies multiple Hierarchical STA Flows, including ETMs, Boundary-Models (for Bottom-Up analysis) and Timing Contexts (for Top-Down analysis) are supported by EDA vendors.
SmartScope Flow discussed in the paper, provides a method to bridge the gap between the flow with timing-based models and Flat STA, with a vision to provide accuracy as that of Flat STA and runtime/memory requirements as that of timing-model based flows.
This paper will showcase:
i) Quantitative analysis of Full Hierarchical Flows, and
ii) A detailed correlation in terms of runtime, memory, and accuracy comparison among different
Hierarchical STA Flows, with Flat STA as the anchor point for comparison.
1. Hierarchical STA with ETMs: Use of extracted timing models for blocks and netlist/spef for
Toplevel for STA. Best in runtime/memory but could show hit on top-block interface.
2. Bottom-Up analysis with Boundary-Models: A hybrid of etm and full verilog, this flow uses a
trimmed down netlist model for sub-blocks which offers faster TAT along with analyzing the
interface timing inaccuracies, if any.
a. Comprehensive QOR comparison (Memory consumption, Runtime, Performance (Accuracy))
across Hierarchical and Flat methodologies
b. Extended Interface model netlist reduction techniques with similar accuracy
c. Debug techniques to handle Clock Mapping issues
3. Top-Down analysis with Timing context Flat FC-STA: Creating context timing in a Full-Chip Flat
STA for blocks and performing Block STA with actual toplevel latencies as constraints. Support
for both SIM and MIM blocks is provided.
4. SmartScope Flows: Closing the loop b/w Bottom-Up and Top-Down approaches by creating a
hand-shake b/w the two flows.
This paper provides data points on a ~150M instance design, in terms of timing correlation and runtime/memory benefits in comparison to flat STA.
Flat STA on big designs comes with a high cost of runtime and memory requirements, which makes flat STA performed at final design closure stage as the optimal situation. Hence, there are methodologies to perform faster STA, for e.g., distributed chip timing analysis and Hierarchical Timing analysis, which can save on runtime & memory requirements, but could show an impact on accuracy.
For flexibility in STA methodologies multiple Hierarchical STA Flows, including ETMs, Boundary-Models (for Bottom-Up analysis) and Timing Contexts (for Top-Down analysis) are supported by EDA vendors.
SmartScope Flow discussed in the paper, provides a method to bridge the gap between the flow with timing-based models and Flat STA, with a vision to provide accuracy as that of Flat STA and runtime/memory requirements as that of timing-model based flows.
This paper will showcase:
i) Quantitative analysis of Full Hierarchical Flows, and
ii) A detailed correlation in terms of runtime, memory, and accuracy comparison among different
Hierarchical STA Flows, with Flat STA as the anchor point for comparison.
1. Hierarchical STA with ETMs: Use of extracted timing models for blocks and netlist/spef for
Toplevel for STA. Best in runtime/memory but could show hit on top-block interface.
2. Bottom-Up analysis with Boundary-Models: A hybrid of etm and full verilog, this flow uses a
trimmed down netlist model for sub-blocks which offers faster TAT along with analyzing the
interface timing inaccuracies, if any.
a. Comprehensive QOR comparison (Memory consumption, Runtime, Performance (Accuracy))
across Hierarchical and Flat methodologies
b. Extended Interface model netlist reduction techniques with similar accuracy
c. Debug techniques to handle Clock Mapping issues
3. Top-Down analysis with Timing context Flat FC-STA: Creating context timing in a Full-Chip Flat
STA for blocks and performing Block STA with actual toplevel latencies as constraints. Support
for both SIM and MIM blocks is provided.
4. SmartScope Flows: Closing the loop b/w Bottom-Up and Top-Down approaches by creating a
hand-shake b/w the two flows.
This paper provides data points on a ~150M instance design, in terms of timing correlation and runtime/memory benefits in comparison to flat STA.
Event Type
Back-End Design
TimeMonday, June 2411:40am - 11:55am PDT
Location2008, 2nd Floor
Back-End Design
Design
Engineering Tracks