Presentation
Parasitic Leakage Detection in Layout Design
DescriptionDetecting and mitigating parasitic leaks in layout designs is critical for ensuring the reliability and performance of integrated circuits (ICs). This presentation introduces a comprehensive approach to identify, analyze, and resolve parasitic leaks, which significantly impact circuit functionality. Our methodology, utilizing TCAD simulation to define parasitic FET conditions and employing Calibre PERC, enabled precise detection and characterization of leakage paths. The validation of this methodology involved establishing a stringent check rule, correlating it with defined parasitic FET conditions, and meticulously applying it within the layout design using Calibre PERC, thereby confirming the methodology's efficacy. Subsequently, this validated approach was applied to three full-chip layout designs, effectively uncovering and addressing over 9000 risky leak spots. Emphasizing the pivotal role of layout design in leak prevention, our integrated approach aims to identify issues early in the design phase. Through this presentation, we aim to offer valuable insights and practical solutions, empowering designers to proactively address parasitic leaks and enhance the reliability and performance of integrated circuits.
Event Type
Back-End Design
TimeTuesday, June 2510:45am - 11:00am PDT
Location2008, 2nd Floor
Back-End Design
Design
Engineering Tracks