Presentation
Towards a memory-address translation representation scheme
DescriptionVerification with application executables is common phase in virtual development kits (VDKs), RTL simulations and emulation. It involves both loading and dumping memory abstractions, usually modelled as 2D arrays, with the application hex images. This is usually acheived in 2 ways (i) frontdoor loading using design modules mimicking real silicon (ii) backdoor loading using external methods such as simulator API to initialize the design in an "image-loaded" state. The former is slow and inefficient since the design spends a lot of time in loading process along with additional design modules for support. The latter can be performed efficiently without additional design modules but requires a lot of platform-specific infrasturcture with memory-dependent details (for ex: ECC, endianness, controller size). In this presentation we argue that a succint representation of such details is possible for most memories. Such a representation is possible because of stereotypical operations on the memory abstractions. We show that tools processing such representations dramatically reduce the maintainable code size.
Event Type
Engineering Track Poster
TimeTuesday, June 255:20pm - 5:21pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP