Presentation
New SoC Creation Flow based on Extraction and recreating from previous SoC
DescriptionSoC creation is done by integrating Logical subsystems using system verilog language. Connectivity between different subsystems is defined by different specs. Some specs are defined in Documents and xls formats which leads to a real challenge to keep Design up to date with developing spec. When moving from one SoC to another and rebuilding with semi-automation, we face a multitude of major bugs. We understood that our current solution based on Verilog-auto features reached its limits.
Through the presented methodology, we build an automated process enabling to: Extract connectivity information from an existing SoC project; Categorize the extracted connectivity, to keep only what is required for the new generation of SoC projects; and Generate the new connectivity.
Defacto customer built this methodology based on Defacto's SoC Compiler APIs which enabled us to generate a full top level in 5 seconds.
We estimate a global reduction of at least 40% of the execution and Man month overall effort.
Through the presented methodology, we build an automated process enabling to: Extract connectivity information from an existing SoC project; Categorize the extracted connectivity, to keep only what is required for the new generation of SoC projects; and Generate the new connectivity.
Defacto customer built this methodology based on Defacto's SoC Compiler APIs which enabled us to generate a full top level in 5 seconds.
We estimate a global reduction of at least 40% of the execution and Man month overall effort.
Event Type
Engineering Track Poster
TimeTuesday, June 255:52pm - 5:52pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP