Presentation
Row-Based Placement and Legalization for Mixed Signal Power Delivery IP in Memory
DescriptionThe turn-around-time for analog IP layout design significantly exceeds that for digital, despite their low quantity. Although automated migration solutions for analog IP have been proposed recently, their practical application is still challenging because even when the schematic is reused, layout reusability is often hindered by changes in design rule, IP boundary, etc. In this work, we propose row-based placement and legalization methodology, focusing on the mixed signal power delivery IP because 1) almost half of the analog circuit is occupied by power delivery IP quantitatively, 2) it is sensitive to parasitic RC rather than analog constraints such as matching. Precisely, it follows the steps, 1) schematic analysis & component generation, 2) component matching with dynamic floorplan adjustment, 3) global placement, 4) legalization for analog components, 5) vertical legalization with row power assignment, and 6) horizontal legalization with well bias alignment. Experimental results demonstrate that the proposed work can generate reasonable initial placement solutions within 1 hour, with up to 150 components. The generated layouts have 4.05% area overhead, 14.67% HPWL increase in average compared with the manual ones, which could be enhanced by the further optimization, either manually or with additional algorithms.
Event Type
Engineering Track Poster
TimeTuesday, June 255:52pm - 5:53pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP