Presentation
Methodology to analyze and optimize SOC performance and cost using function agnostic cycle accurate models
DescriptionBillions of MCUs drive integration of more number of CPUs, DMAs and variety of peripherals at relatively higher performance. While the low-end SOC level performance, throughput requirements was seldom analyzed systematically, it is impractical to ignore these aspects in mid-end to high-end MCUs due to complexity of integration and performance requirements.
We present methodology to address the mentioned problem
- Peripheral model managing internal FIFO reads/writes agnostic of its function of communication/conversion/processing
- System DMA model with customization options to take care of channel priority, channel switching and R/W transfer latency
- Determine throughput at SOC level using above models by running dynamic simulation as per SOC specification
- Optimize internal memory/buffer/FIFO sizes according to model performance which in turn helps to save cost OR
- Analyze possible performance trade-offs for various scenarios with existing buffer/FIFO sizes and clock frequency of operation
In this presentation, we focus on following method -
Holistic simulation environment using cycle accurate C/SystemC models primarily supporting code execution by cycle accurate ARM CPU models. This is scalable to include/exclude other models as per SOC configuration, change peripheral and SOC configuration on need basis, more importantly, evaluate architecture trade-offs very early at the design exploration stage
We present methodology to address the mentioned problem
- Peripheral model managing internal FIFO reads/writes agnostic of its function of communication/conversion/processing
- System DMA model with customization options to take care of channel priority, channel switching and R/W transfer latency
- Determine throughput at SOC level using above models by running dynamic simulation as per SOC specification
- Optimize internal memory/buffer/FIFO sizes according to model performance which in turn helps to save cost OR
- Analyze possible performance trade-offs for various scenarios with existing buffer/FIFO sizes and clock frequency of operation
In this presentation, we focus on following method -
Holistic simulation environment using cycle accurate C/SystemC models primarily supporting code execution by cycle accurate ARM CPU models. This is scalable to include/exclude other models as per SOC configuration, change peripheral and SOC configuration on need basis, more importantly, evaluate architecture trade-offs very early at the design exploration stage
Event Type
Engineering Track Poster
TimeMonday, June 245:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP