Presentation
Safeguarding datapath security requirements through formal verification
DescriptionIn the fast-evolving landscape of modern computing, where the exponential growth of data is ubiquitous, ensuring the confidentiality and integrity of information stands as a paramount challenge. This paper undertakes a comprehensive exploration of data security, employing the lens of formal security verification to address this critical concern. The study meticulously delves into the integration of cutting-edge tools and methodologies, strategically designed to fortify data security in the face of emerging threats.
At its core, this paper centers around the intricate examination of data paths, driven by the imperative to eliminate potential vulnerabilities that could lead to leakage or corruption. Emphasizing the application of formal methods, the research identifies and mitigates threats to data security, with particular attention to the detection of side channels within processor architectures. This holistic approach extends beyond theoretical foundations, encompassing practical applications and an in-depth exploration of formal modeling techniques, symbolic execution, and advanced analysis methods, including static and dynamic analysis. The paper ensures a dynamic exploration that seamlessly combines theoretical insights with practical applications, promising a comprehensive understanding of formal security verification.
At its core, this paper centers around the intricate examination of data paths, driven by the imperative to eliminate potential vulnerabilities that could lead to leakage or corruption. Emphasizing the application of formal methods, the research identifies and mitigates threats to data security, with particular attention to the detection of side channels within processor architectures. This holistic approach extends beyond theoretical foundations, encompassing practical applications and an in-depth exploration of formal modeling techniques, symbolic execution, and advanced analysis methods, including static and dynamic analysis. The paper ensures a dynamic exploration that seamlessly combines theoretical insights with practical applications, promising a comprehensive understanding of formal security verification.
Event Type
Engineering Track Poster
TimeTuesday, June 255:07pm - 5:08pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP