Presentation
Early Clock Tree Power Estimation and Correlation at SoC: A Case Study
DescriptionClock trees significantly contribute to the overall power consumption of a design, accounting for approximately 30-40% of the total power. Effectively estimating and analyzing clock power at the System-on-Chip (SoC) level is crucial for identifying and optimizing weak areas in the design. The identification of power bugs prompts the exploration of various Clock Gating Strategies to enhance power efficiency.
Existing methods for clock tree power estimation at the gate level exhibit dependencies on processes like clock tree synthesis (CTS). However, these dependencies, occurring late in the cycle, hinder design optimization within the strict timelines of the SoC. Close to Base Tape-out (BTO), attempting design optimization becomes more challenging, as changes can disrupt established timelines.
This paper introduces a pioneering workflow for early clock power estimation, providing feedback to cores/IPs at the Register Transfer Level (RTL) stage. This approach aims to address the limitations of current methods and emphasizes a proactive strategy for optimizing clock power in the early stages of design, thus overcoming the constraints imposed by late-cycle dependencies and stringent timelines.
Existing methods for clock tree power estimation at the gate level exhibit dependencies on processes like clock tree synthesis (CTS). However, these dependencies, occurring late in the cycle, hinder design optimization within the strict timelines of the SoC. Close to Base Tape-out (BTO), attempting design optimization becomes more challenging, as changes can disrupt established timelines.
This paper introduces a pioneering workflow for early clock power estimation, providing feedback to cores/IPs at the Register Transfer Level (RTL) stage. This approach aims to address the limitations of current methods and emphasizes a proactive strategy for optimizing clock power in the early stages of design, thus overcoming the constraints imposed by late-cycle dependencies and stringent timelines.
Event Type
Engineering Track Poster
TimeMonday, June 245:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP