Presentation
Design Enablement of 2D/3D Power-Thermal Self-Consistent Analysis
DescriptionIn the last years, CMOS scaling becomes slower than used to be and it becomes more challenging to follow Moore's law. One of the proposed scaling boosters is system level 3D-IC where the vertical dimension is used by stacking dies on top of each other. Fine-pitch 3D interconnects such as wafer-to-wafer hybrid bonding (10-1 µm) leverage the benefits of 3D-IC by reducing the wire length connections, hence improving PPA compared to the 2D counterparts.
Thermal hotspots become more challenging with 3D-IC for two reasons. First, reducing die footprint in 3D stacks leads to increasing the power density. Second, bringing two dies in close proximity leads to heat confinement and poor heat dissipation.
In this work, a thorough 3D thermal analysis is performed on MemPool design. Face-to-face 3D stack of MemPool design leads to maximum temperature increase by 30ºC compared to the 2D counterpart configuration under static power conditions. Increasing temperature escalates the static leakage power and resistance and results in total grid resistance and max IR-drop value to rise by 2.8% and 4.7% respectively.
Cadence Celsius thermal solver and Voltus™ IC power integrity are used in the electrical-thermal co-simulation presented in this work.
Thermal hotspots become more challenging with 3D-IC for two reasons. First, reducing die footprint in 3D stacks leads to increasing the power density. Second, bringing two dies in close proximity leads to heat confinement and poor heat dissipation.
In this work, a thorough 3D thermal analysis is performed on MemPool design. Face-to-face 3D stack of MemPool design leads to maximum temperature increase by 30ºC compared to the 2D counterpart configuration under static power conditions. Increasing temperature escalates the static leakage power and resistance and results in total grid resistance and max IR-drop value to rise by 2.8% and 4.7% respectively.
Cadence Celsius thermal solver and Voltus™ IC power integrity are used in the electrical-thermal co-simulation presented in this work.
Event Type
Engineering Track Poster
TimeMonday, June 245:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP