Presentation
Empowering CDC analysis methodology with root cause analysis
DescriptionCDC static verification tool with machine learning (ML) capability helps engineers with apt root cause analysis (RCA) to bring down the noise in results. An improper constrained design may leak a bug into silicon, or an over constrained design may not lead to verification closure. Often it is required in static methodologies to have an automated data analysis or ML solution which can detect the issues in the CDC setup stage of the design. Using the causality analysis, EDA tools suggest better constraints to report real issues and eliminate noise.
This paper investigates how improper or missed constraints can affect the CDC analysis results and subsequently devises a methodology for an effective use of ML feature in form of causality reports. Firstly, RCA can start from fine tuning the clock constraints with the suggested constraints for the clock tree to maintain an optimal pessimism in CDC analysis. Secondly, engineers should focus on other constraints like stables, constants etc., on data paths as suggested in RCA. Lastly, engineers should investigate other miscellaneous constraints through causality reports to reduce noise. Thus, RCA should be done in a progressive iterative manner for an effective CDC analysis with real issues.
This paper investigates how improper or missed constraints can affect the CDC analysis results and subsequently devises a methodology for an effective use of ML feature in form of causality reports. Firstly, RCA can start from fine tuning the clock constraints with the suggested constraints for the clock tree to maintain an optimal pessimism in CDC analysis. Secondly, engineers should focus on other constraints like stables, constants etc., on data paths as suggested in RCA. Lastly, engineers should investigate other miscellaneous constraints through causality reports to reduce noise. Thus, RCA should be done in a progressive iterative manner for an effective CDC analysis with real issues.
Event Type
Engineering Track Poster
TimeTuesday, June 255:03pm - 5:03pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP