Presentation
Advancing Low Power Design in the Era of Rising Energy Footprints: Insights from IEEE 2416 Standard and Future Extensions
DescriptionIn the current dynamically changing landscape of computing, growth of artificial intelligence (AI) applications have caused an exponential increase in energy consumption, re-emphasizing the need for managing power footprint in chip design. To manage this escalating energy footprint and enabling true system level low power design, modeling standards play a key role to facilitate inter-operability and re-use. The IEEE 2416 system level power modeling standard, introduced in 2019, offers a unified framework spanning system-level to detailed design, facilitating comprehensive low power design for entire systems. This standard also enables efficiency through contributor-based Process, Voltage, and Temperature (PVT) independent power modeling.
The IEEE 2416 standard is currently undergoing several extensions slated for release in 2024. Noteworthy among these extensions is the comprehensive modeling of multiple voltage blocks and precise representations of analog and mixed-signal blocks. We present these upcoming extensions for the first time, highlighting their potential value through a complete system example with processor cores, accelerators, analog and mixed-signal IP.
This presentation offers insights into the practical implementation of forthcoming extensions with examples. We believe that sharing these advancements, coupled with real-world examples, will help the audience gain valuable early details in using the standard for designing low power systems.
The IEEE 2416 standard is currently undergoing several extensions slated for release in 2024. Noteworthy among these extensions is the comprehensive modeling of multiple voltage blocks and precise representations of analog and mixed-signal blocks. We present these upcoming extensions for the first time, highlighting their potential value through a complete system example with processor cores, accelerators, analog and mixed-signal IP.
This presentation offers insights into the practical implementation of forthcoming extensions with examples. We believe that sharing these advancements, coupled with real-world examples, will help the audience gain valuable early details in using the standard for designing low power systems.
Event Type
Engineering Track Poster
TimeMonday, June 245:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP