Presentation
Novel Way of Checking and Analyzing Peak to Peak Voltage Variation Challenges for High Computational Multiprocessors SOC
DescriptionIncreasing functionality of Automotive multiprocessor SOCs has resulted in increasing power grid complexity leading to high voltage-ripple noise caused by simultaneous switching of multiple processor blocks in the SoC. Meeting chip-package-system (CPS) performance targets becomes daunting due to this issue. Designers grapple with the lack of accurate chip models for chip-package-system co-analysis for power integrity signoff involving microsecond long simulations. The conventional Chip Power Model (CPM) falls short in addressing low frequency noise (0.1 – 50 MHz) caused during chip mode-changes over longer durations. Multiprocessor chips have high demand currents that require techniques like clock and power gating to deal with excessive power requirement. However, Dynamic Voltage and Frequency Scaling (DVFS) and clock gating can induce significant simultaneous switching noise (SSN) on VDD. We present here the results of our study that utilized advanced chip power models involving time extensions, stitching of multiple models and modulation of high frequency chip currents over mode-changing low frequency current envelope, to help detect and mitigate high peak to peak voltage variations in our chip-package-system transient analysis with a faster turn-around-time.
Event Type
Engineering Track Poster
TimeMonday, June 245:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP